1. Field of the Invention
The present invention relates to an image data processing apparatus for dividing one page of image data into a plurality of segments for high-speed image data processing.
2. Description of the Prior Art
There is proposed (as in Japanese Patent Laid-Open No. SHO/62-176374) an apparatus that compresses and expands image data at high speed by dividing each page of image data into a plurality of segments and by having each of the segments compressed and expanded by an individual compandor. This applicant has also disclosed a similar image data processing apparatus in Japanese Patent Application No. HEI/3-274667. FIG. 3 is a block diagram of this apparatus.
In FIG. 3, reference numeral 1 is a CPU (central processing unit); 2 is a DMAC (direct memory access controller); 3 is an IIT (image input terminal); 4 is an IOT (image output terminal); 5 is an image memory; 6-1 and 6-2 are compandors; 7 is an image data bus; 8-1 and 8-2 are FIFO (first-in first-out) memories for temporarily storing small quantities of data; 9 is another DMAC; 10 is a local DMA bus; and 11 is a compressed data storage means (e.g., RAM (random access memory)).
The image data entered from the IIT 3 is transferred to the image memory 5 over the image data bus 7. This transfer of the image data is a DMA data transfer performed under control of the DMAC 2. All data transfers in the description that follows are assumed to be DMA data transfers.
In the setup of FIG. 3, one page of image data is divided into two segments. FIG. 4 is a view showing one page of image data divided into two in the image memory 5, the divided images being denoted by numerals 5-1 and 5-2. The image data representing the divided images 5-1 and 5-2 are transferred to the compandors 6-1 and 6-2, respectively. Because one page of image data is divided into two segments that are compressed concurrently by two compandors, the processing time with the setup of FIG. 3 is far shorter than with the typical scheme of a single compandor handling one whole page of image data.
The compressed data from the compandors 6-1 and 6-2 are sent to the FIFO memories 8-1 and 8-2, respectively. From there, the data are moved by DMA transfer to the compressed data storage means 11 over the local DMA bus 10. These DMA data transfers are controlled by the DMAC 9. Before the DMAC 9 can start a DMA data transfer, the DMAC 9 needs to be activated by the CPU 1 executing a program for DMA data transfer start-up. That is, the DMAC 9 needs to be started by software.
FIG. 5(A)-(C) is a set of timing charts depicting typical timings of DMA data transfers. FIG. 5 (A) shows timings of DMA data transfers between the FIFO memories 8-1 and 8-2 on the one hand, and the compressed data storage means 11 on the other in FIG. 3. Specifically, the waveform (a) in FIG. 5 (A) stands for DMA data transfers between the FIFO memory 8-1 and the compressed data storage means 11, and the waveform (b) in FIG. 5(A) represents DMA data transfers between the FIFO memory 8-2 and the compressed data storage means 11. Each shaded portion in the charts indicates the time required to carry out a DMA data transfer.
In the setup above, a scheme is provided whereby the DMAC 9 is started when a predetermined amount of compressed data is accumulated in the FIFO memory 8-1. The predetermined amount of compressed data when accumulated in the FIFO memory 8-1 is transferred therefrom to the compressed data storage means 11. The predetermined amount of data may be half the capacity of the FIFO memory. Likewise, a predetermined amount of compressed data, when accumulated in the FIFO memory 8-2, separately causes the DMAC 9 to start and is transferred thereby to the compressed data storage means 11. The time T.sub.1 in FIG. 5 (A) is the time required by the CPU 1 to start the DMAC 9 (i.e., overhead of the CPU 1).
For data expansion, the compressed data representing the divided images 5-1 and 5-2 in FIG. 4 are sent to the corresponding FIFO memories and compandors for a concurrent expanding process. The concurrent expansion of two image data segments produces one page of image data. Another scheme is devised whereby whenever a predetermined amount of memory space is vacated in either FIFO memory (i.e., half the FIFO memory capacity), the CPU 1 causes the DMAC 9 to start a DMA data transfer from the compressed data storage means 11 to the FIFO memory in question. For data transfer to the other FIFO memory, the CPU 1 separately activates the DMAC 9 to carry out the transfer.
One disadvantage of the above-described prior art apparatus proposed by this applicant is that it takes time to start the DMAC 9 by the CPU 1 every time the FIFO memories 8-1 and 8-2 are switched therebetween for DMA data transfer. The time thus consumed makes it difficult to transfer the data at high speeds.
To reduce the number of times the CPU 1 starts the DMAC 9 requires reducing the number of times the FIFO memories are switched. That in turn requires increasing the capacity of the FIFO memories. However, this measure if implemented would lead to another disadvantage: higher cost.
The above example involves two FIFO memories to deal with two divided images. If each page of image data is divided into more than two segments, the number of FIFO memories will be increased correspondingly. A larger number of FIFO memories entails an increased number of times the DMAC 9 is started. This means that by the time its turn has come to make a DMA data transfer, a particular FIFO memory may well have been filled with compressed data. With the available memory capacity of the FIFO memory thus exhausted, the compandor corresponding to that FIFO memory is stopped because it cannot output compressed data therefrom. That in turn makes it difficult for the apparatus to fully carry out concurrent image data processing at high speed.